The NE555 is configured as an astable multivibrator and produces a rectangular wave at its output, with variable mark-space ratio and variable frequency. This results in timing capacitor C3 (see schema diagram) being alternately charged and discharged; the voltage at pin 2 (THR) of the NE555 swings between one-third of the supply voltage and two-thirds of the supply voltage.
Voltage Inverter Circuit Using IC NE555
In the feedback path NPN transistor T2 has the function of a voltage level shifter, being wired in common-base configuration. The threshold is set by the resistance of the feedback chain comprising resistor R3 and potentiometer P1. When the emitter voltage of transistor T2 is more than approximately 500 mV lower than its base voltage it will start to conduct. Its collector then acts as a current sink. Potentiometer P1 can be used to adjust the sensitivity of the negative feedback schema and hence the final output voltage level.Using T1 as a voltage reference means that the schema will adjust itself to compensate not only for changes in load at K2, but also for changes in the input supply voltage. If K2 is disconnected from the load the desired output voltage will be maintained, with the oscillation frequency falling to around 150 Hz.
A particular feature of this schema is the somewhat unconventional way that the NE555’s discharge pin (pin 7) is connected to its output (pin 3). To understand how this trick works we need to inspect the innards of the IC. Both pins are outputs, driven by internal transistors with bases both connected (via separate base resistors) to the emitter of a further transistor. The collectors of the output transistors are thus isolated from one another [1].
The external wiring connecting pins 3 and 7 together means that the two transistors are operating in parallel: this roughly doubles the current that can be switched to ground.The two oscilloscope traces show how the output voltage behaves under different circumstances. The left-hand figure shows the behaviour of the schema with an input voltage of 9 V and a resistive load of 470 Ω connected to the lower pin of output connector K2. The figure on the right shows the situation with an input voltage of 10 V and a load of 1 kΩ on the lower pin of output connector K2. The pulse width and frequency of the rectangle wave at the output of IC1 are automatically adjusted to compensate for the differing conditions by the feedback mechanism built around T1 and T2.
Because of the voltage drops across the Darlington out-put stage in the IC (2.5 V maximum) and the four diodes (700 mV each) the schema achieves an efficiency at full load (470 Ω between the output and ground) of approximately 50 %; at lower loads (1 kΩ) the efficiency is about 65 %.

